The field of the invention is the formation of a capacitor with increased surface area due to silicon nodules; in particular capacitors for dynamic random access memory (DRAM) integrated circuit devices.
The continued scaling of DRAM cell sizes requires maintaining a sufficiently high storage capacitance per cell. Physical limitations such as high leakage current and excessive failure rate have prevented aggressively reducing capacitor dielectric thickness. Therefore, techniques to increase effective storage surface area are needed for further scaling of DRAMs in the submicron regime.
One such technique involves the use of silicon nodules deposited on the surface of the plate of one of the capacitor plates, thereby increasing the area of the plate. This technique is compatible with existing silicon processing techniques and does not introduce extraordinary challenges to device and tooling integration. The silicon nodules deposited on the capacitor electrode are typically hemispherical in shape. Modulation of their size, shape and density is important for the optimization of capacitance.
There are a variety of conventional techniques for increasing the surface area of a capacitor electrode with Si nodules. In conventional processes, (1) an amorphous Si layer is deposited, (2) it is then seeded and then (3) the film is annealed under high vacuum conditions to form the nodules. Seeding refers to the formation of Si nuclei on the a-silicon film. A significant disadvantage of this technique is that it is not suitable for trench technology in the submicron range because of the loss of available trench diameter with the deposition of the first a-silicon layer (which is typically 100 nm thick). The thick amorphous silicon film is necessary in the conventional scheme because it provides a source from which the silicon nodules may grow and increase the size of the nuclei during anneal.
It is an object of the present invention to provide a method of creating stable Si nodules that may be used to enhance the area of a planar capacitor electrode.
A feature of the invention is the deposition of silicon on a smooth dielectric seed layer.
Another feature of the invention is the use of a thin dielectric layer that is removed in a subsequent high-temperature step.